Semiconductor devices such as logic and memory devices are typically fabricated by a sequence of processing steps applied to a substrate or wafer. The various features and multiple structural levels of the semiconductor devices are formed by these processing steps. For example, lithography among others is one semiconductor fabrication process that involves generating a pattern on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield. As design rules and process windows continue to shrink in size, inspection systems are required to capture a wider range of physical defects on wafer surfaces while maintaining high throughput.
Many different types of inspection systems have adjustable acquisition mode parameters (e.g., data, signal, and/or image acquisition parameters), adjustable defect detection parameters, and adjustable defect classification parameters. Different parameters are used to detect different defects of interest and avoid sources of noise that give rise to unwanted nuisance events. An inspection system with adjustable acquisition mode, defect detection, and classification parameters offers significant advantages to a semiconductor device manufacturer by making it possible for a single tool to successfully discriminate a wide range of defects. However, successful inspection requires correct selection of these parameters. Parameter selection is complicated and unpredictable because wafer characteristics, defect characteristics, process conditions, and noise on wafers may vary dramatically.
For inspection tasks that require identifying defect of interest from nuisance events, a successful inspection recipe for a semiconductor layer should maximize the number of detects of interest (DOI) detected while minimizing the number of nuisance events detected. By extension, for inspection tasks that require binning of defects, a successful inspection recipe for a semiconductor layer should maximize the number of correctly binned defects while minimizing the number of nuisance events detected. Formulating an inspection recipe generally involves tuning the acquisition mode parameters, defect detection parameters, and defect classification parameters separately until the desired result is achieved. This process involves a significant amount of manual effort as combinations of acquisition mode parameters, defect detection parameters, and defect classification parameters are manually considered. In some cases, defect detection parameters may be considered in an automated manner with either the acquisition mode parameters or the classification parameters, but this still requires manual consideration of combinations of parameter sets in two parameter spaces to arrive at a desired inspection recipe.
Accordingly, it would be advantageous to develop methods and/or systems for generating inspection scenarios combining acquisition mode, defect detection, and classification parameters from results of a scan of a wafer without user intervention.